An Efficient Approach for Four-Layer Channel Routing in VLSI Design

A new approach to three- or four-layer channel routing

We present in this paper a new approach to the three or four layer channel routing problem. Since two layer channel routing has been well studied, there are several two layer routers which can produce optimal or near optimal solution for almost all the practical problems. We develop a general technique which transforms a two layer routing solution systematically into a three layer routing solut...

An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing

| Constrained Via Minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for twolayer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.

A Review on Channel Routing On VLSI Physical Design

We know that channel routing is very important problem in VLSI physical design. The main objective of a channel routing algorithm is the reduction of the area of a IC chip. In this paper, we just do a survey on some impotent multi-layer routing algorithms. Here we analyze The Efficient Routing algorithm and resolve horizontal constraints and minimize the net wirelength in a particular model of ...

Design Rules in VLSI Routing

An Efficient Rectilinear Steiner Tree Algorithm for Vlsi Global Routing

As we move to deep sub-micron designs below 0.18 microns, the delay of a circuit, as well as power dissipation and area, is dominated by interconnections between logical elements (i.e. transistors)[1]. The focus of this paper is on the global routing problem. Both global and channel routing are NP-hard[2]; therefore, all existing solution methodologies are heuristics. The main aim is to develop...